Preamble : The 2nd Indian Symposium on Computer Systems (IndoSys) will be held in IIIT, Hyderabad from May 23-24, 2015 as a preamble to IPDPS-2015. It is meant as a forum to bring together faculty, scientists, research scholars and practitioners working on different aspects of computer systems research in Indian institutions. IndoSys offers a forum for discussing contemporary research activities in computer Systems, emerging tools, techniques and platforms, and unique systems research activities within the Indian context. The symposium will also serve to build a critical mass of systems researchers within the country to help further scientific activities in this area. This year we have many invited on areas spanning cloud computing, big data, compilers and parallel programming. Further, special session on technical paper writing will also be conducted. Indosys participants are encouraged to attend IPDPS conference which will be held in Hyderbad from May 25-29, 2015.

Organizing Committee

  • R. Govindarajan, IISc, Bangalore
  • Kishore Kothapalli, IIIT, Hyderabad
  • Yogesh Simmhan, IISc, Bangalore
  • Krishna Nandivada, IIT, Chennai
  • Suresh Purini, IIIT, Hyderabad

Supported By:


  • Keynote Talk: TBD
  • Title: Research Problems in Virtualized Data Centers by Prof.Umesh Bellur, IIT-Mumbai.

    Abstract: With the astonishing speed of cloud adoption, virtualization technology has received a massive shot in the arm as it forms the backbone of cloud data centers. While virtualization has the obvious benefits of allowing heterogeneity of operating systems while permitting cloud managers to utilize physical machines to their fullest, it has created its own set of issues. In this talk we explore problems with virtualization and its usage in cloud data centers that we are working on at IIT Bombay. We broadly classify the work into 4 categories: (a) Hypervisor measurement/characterization and improvements - where we look into issues such as memory sharing between VMs for memory overprovisioning and I/O multiplexing for I/O scalability in virtualized environments. (b) VM Provisioning, Placement and Migration - where we explore issues in power aware provisioning of virtual machines, balanced placement, migration models and the tradeoffs between migration and replication of virtual machines. (c) Performance and Availability modeling and Simulation of cloud environments and (d) Cloud costing and Engineering issues in building and managing large clouds where we look at overheads of cloud managers such as OpenStack and CloudStack.

    Speaker Bio: Umesh Bellur is currently Professor of Computer Science at IIT Bombay where he has been since 2003. His research areas include virtualization and distributed event based systems and autonomic control of these environments. He was the recipient of the IBM Faculty award in 2006 and the SAP Research Innovation award in 2008. He is on the editorial board of the IEEE Transactions on Cloud Computing and is on numerous program committees of top tier conferences such as IEEE Cloud, DEBS and ICPADS. He has 6 US patents and has published over 50 papers in various international journals and conferences. He forms part of the ProVM group at IIT Bombay which includes Profs. Purushottam Kulkarni and Varsha Apte - the group was awarded the IBM Shared University Research grant, a presigious multi-year research grant to look into issues in Cloud computing.

  • Title: GPU Code Generation for Graph Algorithms by Dr.Rupesh Nasre, IIT-Chennai.

    Abstract: Irregular algorithms, that is, algorithms exhibiting data-dependent and therefore statically unpredictable control flow and memory access patterns, are ubiquitous in many problem areas such as social network analysis and machine learning. Such algorithms typically operate on dynamic data structures and are challenging to parallelize. There is growing interest in using GPUs for irregular algorithms and past work has demonstrated their efficacy. However, the need for processing larger graphs poses limitations to existing techniques which implicitly assume that the complete graph resides in the main memory of the system. In this work, we deal with processing graphs that do not fit into GPU memory and develop out-of-core techniques to efficiently model the processing. Parallelizing an irregular algorithm on GPUs is quite challenging and making such an algorithm out-of-core only exacerbates the challenge. Therefore, we propose a domain-specific language to synthesize out-of-core irregular computations for GPUs. The synthesizer takes as input a high-level description of an irregular algorithm and a scheduling policy to efficiently generate CUDA code for out-of-core execution of the algorithm on the GPU. We demonstrate the expressiveness of the synthesizer by automatic generation of out-of-core computations for four graph algorithms, and illustrate that the generated code performs very close to the hand-tuned out-of-core versions.

    Speaker Bio: Rupesh is an Assistant Professor in the CSE department at IIT Madras. He completed PhD from IISc Bangalore and Post-Doctoral Fellowship from the University of Texas at Austin. His research focus is in Compilers and Parallelization.

  • A hands-on tutorial on Big Data will be conducted by Prof.Dinakar Sitaram (PESIT) and Prof.S.Pyne (C.R.Rao Institute).
  • A break-out session to understand and address issues faced by graduate students in their research.


  • Title: High-performance compilation through Domain-Specific Languages: the case of Image Processing Pipelines by Dr.Uday Bondhugula, IISc, Bangalore.

    Abstract: This talk addresses the well-known challenge involved in simultaneously delivering high productivity and high parallel performance on modern multicore architectures -- through the development of domain-specific languages (DSLs) and their optimizing code generators. It presents the domain of Image Processing Pipelines as the motivating case by presenting PolyMage, our DSL and its code generator for automatic and effective optimization of image processing pipelines. PolyMage takes an image processing pipeline expressed in a high-level language (embedded in Python) and generates an optimized C/C++ implementation of the pipeline. We show how certain techniques including those based on the polyhedral compiler framework need to be specialized in order to provide significant improvements in parallel performance over existing approaches including manual, library-based, and that of another state-of-the-art DSL (Halide). More information at Experimental results on a modern multicore system and a short demo will also be presented.

    Speaker Bio: Uday Reddy B is an Assistant Professor in the Department of Computer Science and Automation at the Indian Institute of Science. His research interests are in the development of programming and compiler technologies for multicore architectures, the design of domain-specific languages and optimizing code generators for them, polyhedral compiler framework, automatic parallelization, and high-performance computing in general. He has received several grants and awards for his research, including research grants from Intel Labs, National Instruments R&D, and AMD, an NVIDIA CUDA research center award, and an INRIA Associate Team award. Before joining IISc, he was with the Advanced Compiler Technologies group at the IBM T.J. Watson Research Center, Yorktown Heights, New York. He received his PhD in Computer Science and Engineering from the Ohio State University, and his B-Tech in Computer Science and Engineering from the Indian Institute of Technology, Madras.

  • Session on technical paper writing.
  • Session on parallel programming curriculum development.


We can accommodate only a limited number of participants for logistic reasons. If you already have a travel grant from IPDPS, you can attend the conference. Others, please wait for a confirmation from our side. However, everyone should fill this Google registration form.

NOTE : Registration is not complete and accepted until you receive a confirmation email. Participants will be responsible for making travel and lodging arrangements. However, limited accommodation is available in IIIT on a request basis. Please send an e-mail to for any queries.

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